Gate Array Design of a Scalable Parallel-Accessible Memory Subsystem

Abstract :- This is Electronics project report on “Field-Programmable Gate Array Design of a Scalable Parallel-Accessible Memory Subsystem for Image Feature Extraction”. The purpose of this project is the creation of an advanced and efficient memory subsystem architecture that will improve the Haar processing frame rate without compromising the use of Field-Programmable Gate Array resources. Only a few hardware implementations and embedded system implementations have been published.

Basic modules needed by the Haar algorithm.

The high amount of computing power required to analyze a single image frame is yet to be provided by a small, low-power embedded system. The main idea is to build a new memory subsystem that provides all the feature points needed at any given time and in a single access cycle. When it is compared to current best implementation, this architecture would potentially increase the system’s performance by four times in 80% – 85% of the test cases while maintaining a speedup of one in the remaining 15% – 20%. This new memory subsystem is going to be used in the Haar Window Buer which is the one that supplies the data points to the Haar Stage Classier.

Author:- Castillo, Jhonattan

Source:-usu.edu

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