Design of Reliable and Secure Network-On-Chip Architectures
Abstract: Network-on-Chips (NoCs) became the quality communication platform for future massively parallel systems as a result of their performance, flexibility and measurability blessings. However, reliableness problems led to by scaling within the sub-20nm era threaten to undermine the advantages offered by NoCs. This thesis demonstrates style techniques that address each reliableness and security problems facing fashionable operative architectures.
The reliableness and security drawback is tackled at totally different abstraction levels employing a series of schemes that mix info from the architecture-level similarly as hardware-level so as to combat aging effects and meet secure style stipulations whereas maintaining modest power-performance overheads.
Network-on-Chip (NoC) architectures are widely touted as the most promising design for the communication platform for future many-core systems, primarily due to their scalability. Many-core prototypes such as the Intel 80-core, Intel Single Chip Cloud system and Tilera have already used NoCs as the backbone of communication between their on-chip processors.
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In this context, this dissertation addresses sustainability challenges in NoC architectures while preserving system-level efficiency. Merely optimizing for power-performance efficiency creates a fundamental tension in the NoC design spectrum. Existing state-of-theart techniques for NoCs attempt to tackle this tension in a reactive manner by focusing solely on power-performance until a component failure occurs, after which corrective measures are triggered.
This work presents a series of proactive orthogonal approaches, simultaneously addressing the need for aging-awareness while preserving system power-performance efficiency in NoCs.
This dissertation also demonstrates that under certain situations, aging resilience can be provided in NoCs without sacrificing power-performance. This intriguing property, achieved by recognizing the criticality aspects of on-chip communication, can spawn similar effective techniques in the pursuit of balancing power-performance and robustness in NoC architectures. Use this thesis for your reference and study. All rights reserved to the author of the project.
Author: Dean Michael B Ancajas,
Image Source & Download link: Utah State University