This thesis investigates the use of an FPGA to perform hardware coprocessing in a JPEG2000 implementation. JPEG2000 is the next-generation image compression standard developed by the Joint Photographic Experts Group. It is superior to the original JPEG standard in terms of performance and functionality. The thesis aims to provide VHDL modules that can be used to accelerate an existing software implementation of JPEG2000.
The “JasPer” software was selected as the candidate for hardware coprocessing. (JasPer is an open-source JPEG2000 implementation developed by Image Power, Inc. and the University of British Columbia). A detailed set of timing profiles is presented for the JasPer code. From these profiles, the arithmetic encoding stage of the JPEG2000 algorithm was selected for implementation in hardware.
A VHDL implementation of the JPEG2000 arithmetic encoder is presented, suitable for implementation on an FPGA. This VHDL code conforms to the specification of the arithmetic encoder in the standard. The design presented has been verified in simulation. As a consequence of this work, a JasPer variant that uses hardware coprocessing is made possible. Further work is proposed that would involve programming an FPGA with these VHDL modules, for complete system integration.
Author:- Edward James Brennan
Source:-University of Queensland